The present invention relates generally to the field of semiconductor manufacturing, and more particularly, to the field of integrated circuit metrology for evaluating and improving the critical dimension uniformity of features formed on semiconductor wafers.
Current semiconductor fabrication design rules allow for high density and performance associated with ultra large scale integration (ULSI) devices having submicron features, increased transistor and circuit speeds and improved reliability. These design rules define the space tolerances between devices and interconnecting lines and the widths of the lines themselves, to ensure that the devices or the lines do not overlap or interact with one another in undesirable ways. The design rule limitation or the critical dimension (“CD”) defines the minimum width of a line or the minimum space between two lines permitted in the fabrication of devices.
The CD for most ULSI applications is on the order of a fraction of a micron. In CMOS technology, for instance, the transistor's gate structure is very critical. This is because the gate width determines the channel length and the channel length affects chip speed. It is projected that the critical dimension for the 16-Gbit DRAM will be 0.1 μm in the year 2006.
Frequently, CD error or variation exists which indicate some instability in a critical part of the semiconductor manufacturing process; such CD error may come from any number of sources, such as optical (e.g., lens field curvature or lens aberration in a photolithography system), mechanical, and chemical (e.g., thickness non-uniformity of resist coating and anti-reflection coating (ARC)). With reduced geometries and increased process complexity, circuit pattern defects occur more frequently and these in turn often adversely affect the performance of finished semiconductor devices. This condition makes defect detection on patterned wafers all the more critical. Early detection, therefore, is essential to gain advanced information about the manufacturing process and device performance and improve CD uniformity.
For these reasons and other reasons that will become apparent upon reading the following detailed description, there is a need for a method of controlling the critical dimension uniformity of features on wafers.